Commit 59c080ede9400a07410b3ce813e08acbe71e5e3f

Authored by Oleh Kosan
0 parents
Exists in master

project's directory structure created

design/.gitattributes 0 → 100644
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  1 +# Set the default behavior, in case people don't have core.autocrlf set.
  2 +* text=auto
  3 +
  4 +# Explicitly declare text files you want to always be normalized and converted
  5 +# to native line endings on checkout.
  6 +*.c text
  7 +*.h text
  8 +*.sh text
  9 +*.cpp text
  10 +*.hpp text
  11 +*.html text
  12 +*.sv text
  13 +*.v text
  14 +*.md text
  15 +*.tcl text
  16 +*.txt text
  17 +*.qip text
  18 +*.rpt text
  19 +*.qpf text
  20 +*.qsf text
  21 +
  22 +# Declare files that will always have CRLF line endings on checkout.
  23 +*.sln text eol=crlf
  24 +
  25 +# Denote all files that are truly binary and should not be modified.
  26 +*.png binary
  27 +*.jpg binary
  28 +*.pdf binary
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design/.gitignore 0 → 100644
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  1 +# Working with Altera Quartus II (Q2) and do proper versioning is not that easy
  2 +# but if you follow some rules it can be accomplished. :)
  3 +# This file should be placed into the main directory where the .qpf file is
  4 +# found. Generally Q2 throws all entities and so on in the main directory, but
  5 +# you can place all stuff also in separate folders. This approach is followed
  6 +# here. So when you create a new design create one or more folders where your
  7 +# entities will be located and put a .gitignore in there that overrides the
  8 +# ignores of this file, e.g. one single rule stating "!*" which allows now all
  9 +# type of files. When you add a MegaFunction or another entity to your design,
  10 +# simply add it to one of your private folders and Q2 will be happy and manage
  11 +# everything quite good. When you want to do versioning of your generated
  12 +# SOF/POF files, you can do this by redirecting the generated output to an own
  13 +# folder. To do this go to:
  14 +# "Assignments"
  15 +# -> "Settings
  16 +# -> "Compilation Process Settings"
  17 +# -> "Save project output files in specified directory"
  18 +# Now you can either place a .gitignore in the directory and allow the following
  19 +# list of types:
  20 +# !*.sof
  21 +# !*.pof
  22 +# or you create an own submodule in the folder to keep binary files out of your
  23 +# design.
  24 +
  25 +# Need to keep all HDL files
  26 +# *.vhd
  27 +# *.v
  28 +
  29 +# ignore Quartus II generated files
  30 +*_generation_script*
  31 +*_inst.vhd
  32 +*.bak
  33 +*.cmp
  34 +*.done
  35 +*.eqn
  36 +*.hex
  37 +*.html
  38 +*.jdi
  39 +*.jpg
  40 +*.mif
  41 +*.pin
  42 +*.pof
  43 +*.ptf.*
  44 +*.qar
  45 +*.qarlog
  46 +*.qws
  47 +*.rpt
  48 +*.smsg
  49 +*.sof
  50 +*.sopc_builder
  51 +*.summary
  52 +*.tcl
  53 +*.txt # Explicitly add any text files used
  54 +*~
  55 +*example*
  56 +*sopc_*
  57 +# *.sdc # I want those timing files
  58 +
  59 +# ignore Quartus II generated folders
  60 +*/db/
  61 +*/incremental_db/
  62 +*/simulation/
  63 +*/timing/
  64 +*/testbench/
  65 +*/*_sim/
  66 +
  67 +*.sublime-workspace
0 68 \ No newline at end of file
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design/README.md 0 → 100644
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  1 +# Erter CPU project
  2 +
  3 +The project is about creating simple CPU. The following entities will be designed:
  4 + * <TODO>
  5 + * <TODO>
  6 + * <TODO>
  7 +
  8 +Supported FPGA models: <todo insert full model here>
  9 +
  10 +> Synthesier and programmer version required:
  11 +* Xilinx ISE <TODO insert link here>
  12 +* Quartus II version from 7.0 to 10.1 inclusive. Download it from altera [download center](https://www.altera.com/downloads/download-center.html).
  13 +
  14 +## How to start
  15 +Use git-bash, cygwin or nix-shell to navigate to project dir. Then in your shell type:
  16 +```bash
  17 +source sourceme
  18 +```
  19 +
  20 +Now you have access to all the command line tools and scripts available under /scripts directory. Some of them are:
  21 +```bash
  22 +prog # run FPGA programmer
  23 +sim # run RTL simulation with specified stimulus
  24 +vlint # run static analysis report generation for code
  25 +```
  26 +
  27 +### Useful links:
  28 +
  29 + * [dedicated wiki page](https://simple.endrobene.com/erter/index.html) on wiki.endrobene.com
  30 + * [markdown-it](https://github.com/markdown-it/markdown-it) for Markdown parsing
  31 + * [online EDA playground](http://edaplayground.com/) SystemVerilog code and testbench editor
  32 + * [online Verilog tutorials](www.asic-world.com/verilog/) at asic-world.com
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design/docs/_remove_ 0 → 100644
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design/implementation/_remove_ 0 → 100644
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design/scripts/prog 0 → 100644
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  1 +#!/bin/bash
  2 +
  3 +# TODO: add script body here
0 4 \ No newline at end of file
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design/scripts/sim 0 → 100644
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  1 +#!/bin/bash
  2 +
  3 +# TODO: add script body here
0 4 \ No newline at end of file
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design/scripts/vlint 0 → 100644
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  1 +#!/bin/bash
  2 +
  3 +# TODO: add script body here
0 4 \ No newline at end of file
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design/src/_remove_ 0 → 100644
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design/testbench/_remove_ 0 → 100644
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design/testbench/execution_tb/_remove_ 0 → 100644
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docs/_remove_ 0 → 100644
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docs/datasheets/cyclone1/ep1c3Schematics.pdf 0 → 100644
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docs/specification/_remove_ 0 → 100644
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model/_remove_ 0 → 100644
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shared/_remove_ 0 → 100644
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sourceme 0 → 100644
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  1 +#!/bin/bash
  2 +
  3 +printf "Adding toolset to PATH, so that programming and simulation is well ran from git bash\n"
  4 +
  5 +echo "Script executed from: ${PWD}"
  6 +
  7 +MY_PROJECT_HOME=`realpath $(dirname $0)`
  8 +echo "Project home: ${MY_PROJECT_HOME}"
  9 +
  10 +# Adding scripts to system PATH
  11 +MY_SCRIPTS_HOME=$MY_PROJECT_HOME/scripts/
  12 +
  13 +export PATH=$MY_SCRIPTS_HOME:$PATH
  14 +
  15 +
  16 +
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verification/_remove_ 0 → 100644
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